1. Field of the Invention
The present invention relates to a dynamic random access memory (hereinafter called "a dynamic RAM") and particularly a dynamic RAM comprising a memory cell including a capacitor for data storage and a transfer gate transistor for coupling the capacitor to a write-in data transmitting line.
2. Description of the Related Art
Semiconductor memories have heretofore been used in various fields with the advancement of the semiconductor technology.
One of such semiconductor memories is a dynamic RAM which utilizes a capacitor for data storage. Dynamic RAM is roughly grouped into two types depending on the memory cell structure. A memory cell of one type has one capacitor and one transistor, and is called one transistor/one capacitor type cell. A memory cell of the other type has three transistors and one capacitor, and is called three transistor/one capacitor type cell. Dynamic RAM has high integration density as compared to static RAMs, and is popularly employed in various fields requiring large storage capacity. One of the fields to which such semiconductor memories are applied is an image processing field. In the image processing field, image information is processed in a digital form. However, when it is desired to process digital image information at high speed, semiconductor memories are required which can execute writing of data therein and reading of data therefrom in a separate manner. One of such semiconductor memories is a dynamic RAM in which a data write path and data read path are separately provided.
FIG. 1 is a schematic diagram showing one example of the overall structure of a conventional dynamic RAM. The dynamic RAM shown in FIG. 1 is a serial access memory and is so constructed that address of the memory cell in which data is to be written and from which it is to be read out is incremented or decremented successively.
Referring now to FIG. 1, the conventional dynamic RAM includes a memory cell array 1 having a plurality of memory cells arranged in M rows and N columns, a write row/column pointer 2 for generating data write addresses WW and WP for specifying a memory cell to be subjected to data writing in the memory cell array 1 in response to a write enable signal WE, a write address reset signal WRST and a write clock signal WCK, a read row/column pointer 3 for generating data read addresses RW and RP for specifying a memory cell to be accessed for data reading in response to a read enable signal RE, a read address reset signal RRST and a read clock signal RCK, a write control circuit 4 activated in response to the write enable signal WE for generating internal write data corresponding to externally applied write data D.sub.I so as to transmit the same to the addressed memory cell, and a read control circuit 5 activated in response to the read enable signal RE for reading data from the addressed memory cell thereby to produce external read data D.sub.o.
When the write enable signal WE is in an active state, the write row/column pointer 2 serves to increment or decrement the write addresses WW, WP successively in response to the write clock signal WCK. When the write address reset signal WRST is brought into an active state, the write row/column pointer 2 is initialized, so that the write address is reset to an initial value, for example, address "0", and writing of data into a memory cell is inhibited. In addition, the write clock signal WCK designates the timing for writing data into a memory cell, i.e., the timing for introducing externally applied write data D.sub.I into the inside of the device. The write address WW specifies memory cells corresponding to one row, which are to be subjected to data writing in the memory cell array 1, and the write address WP designates memory cells corresponding to one column, which are to be subjected to data writing in the memory cell array 1.
When the read enable signal RE is in an active state, the read row/column pointer 3 serves to increment or decrement the read address RP, RW successively in response to the read clock signal RCK. When the read address reset signal RRST becomes an active state, the read row/column pointer 3 is initialized, so that the read address is reset to an initial value, for example, address "0", and reading of data from a memory cell is inhibited. The read clock signal RCK specifies the timing for reading data from the memory cell, i.e., the timing for outputting the read data D.sub.o to the outside of the device. In addition, the read address RW designates memory cells corresponding to one row in the memory cell array 1, while the read address RP specifies memory cells corresponding to one column in the memory cell array 1.
The write control circuit 4 may include only an input buffer, which directly receives an externally applied write data D.sub.I, for generating internal write data therefrom, or may include the input buffer and a write circuit with large driving capability which receives output data from the input buffer for performing further buffer processing of the same and for transmitting the processed data to the internal write data transmission line (selected column).
In general, the read control circuit 5 includes a read driver for detecting and amplifying data read from a selected memory cell and an output buffer for producing an external read data D.sub.o in response to an output from the read driver.
FIG. 2 is a circuit diagram showing a main portion of the dynamic RAM of FIG. 1 in connection with writing of data therein. In the FIG. 2, the dynamic RAM used to write data therein and read out data therefrom on one bit unit is shown by way of illustrative example. The structure of the dynamic RAM of such three transistors/one capacitor type is described in the technical article entitled "Introduction to MOS LSI Design", by J. Maber, and translated by T. Sugan et al., published by Sangyo Tosho Kabushiki Kaisha, Apr. 20, 1984, FIG. 5.28.
Referring to FIG. 2, a write row line WW and a read row line RW are arranged along the row direction of the memory cell array 1. A write row address WW is transmitted on the write row line WW while a read row address RW is transmitted on the read row line RW. Three write row lines RW are shown in FIG. 2, and three read row lines RW are also illustrated in the same figure. However, the write row line WW and the read row line RW are shown generically for respective row lines. A description will be made below with signal lines and signals transmitted on the signal lines designated with like reference characters.
A write bit line WB for transmitting internal write data therethrough and a read bit line RB for transmitting internal read data thereon are arranged in a column direction of the memory cell array 1. The bit lines WB and RB are also indicated generically for respective bit lines shown in FIG. 2.
A memory cell 100 is disposed at the intersection of the row line WW (or RW) and the bit line WB (or RB). In order to select 1-bit memory cell, an AND circuit 150 is provided for each memory cell. The AND circuit 150 has one input receiving a write address (a write row selection signal) WW and the other input receiving a write column address (a write column selection signal) WP. In addition, the AND circuit 150 produces a selection word signal WW'.
Each of the memory cells 100 has the structure of three transistors/one capacitor type and includes n-channel MOS transistors (n-channel insulated gate type field effect transistors, which are hereinafter called merely "nMOS transistors") 11, 12, 13, and a capacitor 14. The capacitor 14 serves to store information in the form of the electric charge therein. The nMOS transistor 11 is brought into ON state in response to the selection word signal WW' to connect the capacitor 14 to the write bit line WB. The nMOS transistor 13 receives at a gate thereof the information (charge potential) stored in the capacitor 14 to amplify the information stored in the capacitor 14. In addition, the nMOS transistor 12 is turned on in response to the read row address (read row selection signal) to transmit an output from the amplifying nMOS transistor 13 to the read bit line RB.
In order to transmit write data to a selected memory cell, there are provided nMOS transistors Q1, Q2 which are brought into a conductive state in response to the write column selection signal WP and connect the write bit line WB to an internal write data transmission signal line IL.
In order to select memory cells corresponding to one column upon reading, there are provided nMOS transistors Q3, Q4 which are brought into an ON state in response to the read column address (read column selection signal) RP and serve to connect a corresponding read bit line RB to an internal read data transmission signal line OL.
The internal write data transmission signal line IL is provided with a write driver 40 for generating internal write data in response to externally applied write data. The write driver 40 may be an input buffer itself or may be a circuit for buffering an output from the input buffer so as to generate internal write data therefrom. The write driver 40 has a p-channel insulated gate type field effect transistor (hereinafter called merely "pMOS transistor") T1 and an nMOS transistor T2 to form a CMOS inverter. The write driver 40 serves to invert a write data D.sub.I for transmission onto the internal write data transmission signal line IL.
The internal read data transmission signal line OL is connected to an output driver where the internal read data is detected and amplified to be outputted as external read data D.sub.o to an external device via an output buffer. A description will now be made of its operation.
Let's now consider where data representative of logic "1" is written into a memory cell 100 arranged at the position of n-th row and k-th column. It is assumed that logic "1" corresponds to the potential level indicated by "H" substantially equivalent to the level of the operating power supply voltage Vcc, while logic "0" corresponds to the potential level indicated by "L" substantially equivalent to the level of a second operating power supply voltage Vss such as the ground potential.
The write data D.sub.I of logic "0" is first supplied to an input of the write driver 40. This write driver 40 is comprised of an inverter and serves to transmit internal write data of logic "1" onto the internal write data transmission signal line IL.
The write row/column pointer 2 is responsive to the write clock signal WCK for raising the write column selection signal WPk to "H", so that the nMOS transistor Q1 is turned on. As a consequence, the internal write data of logic "1" on the internal write data transmission signal line IL is transmitted onto the write bit line WBk.
Then, a write row selection signal WWn on a write row line WWn is raised to "H". Since the write column selection signal WPk of "H" has already been applied to one of the inputs of the AND circuit 150, a write word signal WW'n of "H" is outputted from the AND circuit 150 so that a transistor 11 in the memory cell 100 arranged at the position of n-th row and k-th column is brought into an ON state. Thus, one electrode (storage nodes) N of the capacitor 14 is connected to the write bit line WBk and the internal write data of logic "1" is written or stored in the capacitor 14. As a consequence, the potential at the storage node N of the capacitor 14 is charged to the level of the power supply voltage Vcc.
In each of the memory cells on other rows and columns, an output from a corresponding AND circuit 150 is at the level of "L" and the transistor 11 in each of the memory cells is kept in an OFF state. As a consequence, the erroneous writing of data into other memory cells is inhibited. Thereafter, the write row selection signal WWn and the write column selection signal WPk fall to "L". The writing operation of the internal write data representative of logic "1" into the memory cell is terminated through the above-described operation.
When it is desired to write internal write data of logic "0" into a memory cell, data indicative of logic "1" is transmitted to the input of the write driver 40, and the same operation as described above is repeatedly executed. The operation of reading of data from the memory cell will now be described by way of an example in which data is read from a memory cell arranged at the position of n-th row and k-th column.
A read row selection signal on a read row line RWk is first raised to "H". Thus, data in memory cells corresponding to one row, which are connected to the read row line RWk, are transmitted over corresponding read bit lines RB. When data of logic "1" has been stored in the capacitor 14 in the memory cell, the amplifying transistor 13 is in an ON state. At this case, a read bit line RBk is connected to the ground potential Vss via the nMOS transistor 12 and the internal read data representative of logic "0" is transmitted onto the read bit line RBk.
When data of logic "0" has been stored in the capacitor 14 of the memory cell, the transistor 13 is in an OFF state and the signal potential at the read bit line RBk becomes the level of the power supply voltage Vcc corresponding to logic "1". Although not shown clearly in FIG. 2, the read bit line RB is provided with a precharge transistor for precharging the read bit line RB up to the level of the power supply voltage Vcc. Thus, each read bit line RB is precharged to level of the power supply voltage Vcc before reading of data.
Upon determination of the signal potential at the read bit line RB, a read column selection signal RPk is raised to "H". As a consequence, the nMOS transistor Q3 is turned on and the read bit line RBk is connected to the internal read data transmission signal line OL, so that the signal potential at the read bit line RBk is transmitted onto the internal read data transmission signal line OL. The signal potential at the internal read data transmission signal line OL is detected and amplified by the output driver, and then it is delivered as external read data D.sub.o to an external device via the output buffer.
A write row/column address and a read row/column address are generated in response to the write clock signal WCK and the read clock signal RCK. The clock signal WCK and RCK also control the timing for writing data into a memory cell and reading data therefrom. Thus, if the triggering timing (timing for triggering row/column selection and writing/reading of data in and from a memory cell) between the write clock signal WCK and the read clock signal RCK is set so as to be different from each other, the writing and reading of data in and from the same memory cell can substantially be executed simultaneously. It is therefore possible to obtain a dynamic RAM which can asynchronously and independently execute the operation of writing and reading of data in and from the memory cell.
Where the aforementioned dynamic RAM is a serial access memory, each of memory cells arranged over the range from a 1st row to an Mth row within a 1st column is selected successively and subsequently each of memory cells arranged over the range from the 1st row to the Mth row within a second column is selected successively. When this operation is repeated to select an memory cell arranged at the position of Mth row and Nth column, it is performed again to select a memory cell arranged at the position of 1st row and 1st column. This dynamic RAM can also function as an LIFO (Last in, First out) memory or FIFO (First in, First out) memory.
A plurality of memory cells are connected to a single write bit line WB. When the dynamic RAM has the storage capacity of, for example 4160 words (1 word size of 8 bits), the memory cell array has memory cells arranged in 130 rows.times.32 columns (one column size of 8 bits) and 130 memory cells are connected to each write bit line. Therefore, a significantly large parasitic capacitance is associated with the write bit line WB and the wiring resistance also exists therein. In order to eliminate the influence of RC delay caused by the parasitic capacitance and the wiring resistance and to change the signal potential at the write bit line WB at high speed, it is required to provide the write driver 40 having large driving capability. When it is desired to transmit the internal write data onto the write bit line WB using such a write driver 40 as referred to above, there is a possibility that data of logic "1", which has been stored in a memory cell, is destroyed. A description will be made in detail below on the reasons or circumstances on the matter referred to above.
FIG. 3 is a partial cross-sectional view showing the structure of a single memory cell in connection with writing of data. In the FIG. 3, a writing memory cell transistor 11 comprises a p.sup.- semiconductor substrate 200
having a low impurity concentration, n.sup.+ impurity regions 201, 202 formed in predetermined regions on the p.sup.- semiconductor substrate 200, a gate insulating film 205 formed on the surface of the semiconductor substrate 200 between the impurity regions 201 and 202, a gate electrode 203 comprised of, for example, polysilicon, which is formed on the gate insulating film 205.
The impurity region 201 is connected to the write bit line WB via a wiring layer formed of, for example, aluminum. The gate electrode 203 is connected to the write word line (output of the AND circuit 150) WW' through an interconnection layer formed of, for example, aluminum.
The capacitor 14 in each of the memory cells includes the semiconductor substrate 200, a capacitor insulating film 206 formed on the semiconductor substrate 200, an electrode layer 204 formed of, for example, polysilicon, which is formed on the capacitor insulating film 206. The semiconductor substrate 200 constitutes one electrode of the capacitor 14 and the electrode layer 204 constitutes a storage node of the capacitor 14. The electrode layer 204 is electrically connected to the impurity region 202 through the interconnection layer N formed of, for example, aluminum.
The semiconductor substrate 200 is biased with the ground potential Vss via a p.sup.+ impurity region 207 having a high impurity concentration, which is formed on a predetermined surface region of the semiconductor substrate 200, and an interconnection layer 211 formed of, for example, aluminum.
In order to electrically separate respective cells on the surface region between the transistor 11 and the capacitor 14, an field insulating film 210 for the cell isolation is formed.
In the structure of the memory cell having the insulated gate type field effect transistors, there is formed a parasitic bipolar transistor Tp in which the impurity region 201 serves as the emitter, the impurity region 202 serves as the collector and the semiconductor substrate 200 serves as the base.
Let's now consider where date of logic "0", i.e., a signal having the level of the potential Vss is transmitted to the write bit line WB from the write driver 40. The write bit line WB also has the parasitic inductance as well as the parasitic capacitance and the wiring resistance. Due to existence of the parasitic capacitance and inductance, some undershoots occur as shown in FIG. 4 when the potential at the write bit line WB falls from "H" to "L", thereby causing the time interval during which the potential at the write bit line WB becomes lower than the potential Vss. The magnitude of the overshoot may be significant since, as mentioned earlier, driving capability of the driver 40 is high. Furthermore, means for reducing the inductance of drive lines as a means to reduce the size of ringing signal is known.
Since the level of the semiconductor substrate 200 is equal to that of the ground potential Vss, the base-to-emitter of the parasitic bipolar transistor Tp is biased in the forward direction due to the undershoots referred to above, so that the base current flows from the base of the parasitic bipolar transistor Tp to the emitter thereof and the parasitic bipolar transistor Tp is turned on.
Accordingly, even when the potential at the gate electrode 203 is "L" corresponding to the level of the ground potential Vss in a non-selected memory cell, the signal charge at the storage node N is delivered out to the write bit line WB through the parasitic bipolar transistor Tp if data of logic "1" has been stored in the storage node N. Thus, if the data of logic "1" has been stored in the capacitor 14 of the non-selected memory cell, a charge potential at the storage node N is reduced.
When the charge potential at the storage node N becomes lower than the threshold voltage of the amplifying transistor 13, the transistor 13 to be turned on upon reading of data is turned off and erroneous data is read out.
The more the dynamic RAM operates at high speed, and with the capacity of the memory device increased, the effect of parasitic inductance becomes greater, so that the undershoot in the signal potential at the write bit line WB excessively appears correspondingly.
Even when the charge potential of the capacitor 14 does not exceed the threshold voltage of the transistor 13, the electric charges stored in the capacitor 14 leak to the write bit line WB due to turn-on of the parasitic bipolar transistor caused by such undershoot as referred to above, so that the characteristic of holding the electric charges in the memory cell is deteriorated.
When it is desired to write data of logic "0" into a memory cell, the potential at the write bit line WB falls from "H" to "L" in FIG. 4. This shows that if the dynamic RAM is a serial access memory, the internal write data during previous write cycle becomes data of logic "1" and subsequently, the internal write data of logic "0" is transmitted to the write bit line WB because each of memory cells arranged on a single column (write bit line) is accessed successively.
In a dynamic RAM in which the write bit line is precharged to "H" level or the intermediate potential level before writing of data therein as an alternative to such a serial access memory as referred to above. The undershoot as described above, will occur in this bit line upon writing of the internal write data into the write bit line.
In order to prevent leakage of storage charges caused by such undershoot as referred to above, possible consideration is that the potential at the substrate 200 is biased to a negative potential V.sub.BB. However, this dynamic RAM is generally integrated on the same substrate with other logic processing circuitry. When the bias voltage V.sub.BB is applied to the substrate 200, the logic processing circuit fails to operate at high speed because the threshold voltage of the MOS transistor is raised due to the back gate bias effect (substrate effect). It is not desirable to provide a on-chip V.sub.BB generator in view of a chip occupation area , its current consumption, and cost/performance thereof.
Such leakage of data charges due to the undershooting also occurs in one transistor/one capacitor type cell.